Synthesis of Low Power Sequential Circuit

Low power design is most required now a days due to scaling down the technology where minimizing the voltage level is the most effective way to minimize the power consumption. This paper presents a double pulse flip flop implemented using 0.18 μm technology. The proposed flip flop avoids unnecessary switching and stacking of transistors and thus consume less power as compared to conventional flip flops. A pulse generator is used to generate less width pulses, which will be helpful in increasing the clock frequency. A low power sequential circuit is designed and simulated using Mentor Graphics tools.